View MB3836_4870965.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds04-27707-2e fujitsu semiconductor data sheet assp for power supply applications (for secondary battery) li-ion battery protection ic MB3836 n description the MB3836 is a lithium-ion battery protection ic for three cells series lithium-ion battery pack in a notebook pcs. this ic supports charging at 12.6 v and detects an over-charge, over-discharge, and over-current to control charging and discharging. the ic has a built-in function that makes the battery rechargeable even when the battery voltage has decreased to 0 v. upon detection of an over-discharge from the lithium-ion battery, the ic outputs a preliminary signal to stop discharging. this feature allows the notebook pc to save its memory data to hard disk. in addition, the ic allows the battery to be used up to the over-discharge level of each cell, increasing the operating time. after detecting an over-discharge, the ic disconnects all of its biases so that its current consumption becomes 0 m a. the ic can therefore make the battery pack rechargeable even when it has been left for an extended period of time with the output disconnected due to over-discharging. the battery can also be set into a quasi-over-discharged state even when the cell voltage is equal to or greater than the over-discharge detection voltage. when the notebook pc is shipped, the ic can prevent the battery pack from being discharged and turn off its bias sources, allowing the battery pack to be stored for a long time. the ics remote on/off function can turn off the output from the detached battery pack without the need for an external logic circuit or any mechanism on the notebook pc. this prevents the output from being short-circuited by a malfunction and facilitates the handling of the battery pack itself. the MB3836 is the best ic for protecting the lithium-ion battery pack used for a notebook pc. n pac k ag e 20-pin plastic ssop (fpt-20p-m03)
MB3836 2 n features ? power supply voltage range : 6 v to 13.5 v ? high-precision over-charge detection voltage : 4.325 v 0.025 v ? circuit power consumption after detecting over-discharge : 0 m a (typ) ? built-in quasi-over-discharge function ? built-in pre-alarm function before shutting down of over-discharge ? built-in remoting on/off function ? built-in over-discharge current detecting function with 2-step delay time : vth = 300 mv ? 7 ms (typ) : vth = 600 mv ? 500 m s (typ) ? built-in charge recovery function for 0 v cell n pin assignment (top view) (fpt-20p-m03) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ocv : cout : dout : n.c. : vs : vcc : bath : batm : batl : gnd : : outon : pf : pdwn : msw2 : msw1 : vmon : covt : coct : cuvt : cpdt
MB3836 3 n pin descriptions pin no. pin name i/o description 1 ocv i over-current state and discharging/charging state detection terminal 2 cout o pch mos control output terminal for charging control switch 3 dout o pch mos control output terminal for discharging control switch 4n.c. ? no connection 5 vs o h level output terminal for remoting on function 6vcc ? power supply terminal 7 bath i battery connection terminal 8 batm i battery connection terminal 9 batl i battery connection terminal 10 gnd ? gnd terminal 11 cpdt ? capacitor connection terminal for setting power-down delay time 12 cuvt ? capacitor connection terminal for setting pf output delay time 13 coct ? capacitor connection terminal for setting over-current detection time 14 covt ? capacitor connection terminal for setting over-charge detection time 15 vmon o output terminal of monitoring cell voltage 16 msw1 i switching signal of monitoring cell voltage input terminal 17 msw2 i 18 pdwn i power down signal input terminal after input h level, latch 3 will be set, dout=h level, and ocv=l level. at this time, all battery connecting terminal will be released, and all bias will be set off. 19 pf o pf signal output terminal 20 outon i remoting on signal input terminal after input l level, the bias of over-charge detection block will be set off. at this time, dout and cout value will be equal to h level. msw1 msw2 vmon output cell voltage input block sw ll ? depend on over-charge detection block l h h cell voltage off h l m cell voltage off h h l cell voltage off
MB3836 4 n block diagram - + 1 1 1 + - + - + - - - - + 6 7 8 9 10 15 16 17 13 14 11 12 18 19 20 5 1 2 3 vcc bias on/off 100 k w 100 k w 100 k w bath batm batl gnd vmon msw1 msw2 coct covt cpdt cuvt pdwn pf outon vs ocv cout dout 300 mv 600 mv 4.325 v ( 0.6%) 2.75 v ( 2%) latch2 latch1 latch3 bias on/off 600 w - + (7 ms) (500 m s) pf output time (2 s) [ cell voltage input block] [over-discharge detection, and power fail circuit block] [remote on circuit block] delay circuit [over-current detection block] delay circuit (23 ms) reset decoder reference voltage block power down delay time (20 s) [cell voltage moni- toring block] [over-charge detection block] reset reset
MB3836 5 n absolute maximum ratings * : when mounted on a 10 cm square double-sided epoxy board. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol conditions rating unit min max power supply voltage v cc ?? 20 v input voltage v i bath, ocv, pdwn, outon, pf, msw1, msw2 terminals ? 20 v collector output voltage v o cout terminal ? 25 v output current i o dout, cout terminals (dc) ? 2ma peak output current i o dout, cout terminals duty = t on / t ? 2 / duty ma power dissipation p d ta + 25 c ? 540 * mw operating temperature ta ?- 30 + 85 c storage temperature tstg ?- 55 + 125 c parameter symbol conditions value unit min typ max power supply voltage v cc ? 6.0 12.6 13.5 v input voltage v i ocv, pdwn, outon, msw1, msw2 terminals 0 ? 18 v output current i o vs terminal - 10 ? 0ma external ocv terminal resistor r ocv ??? 10 w capacitor for setting delay time c ovt ? 220 10000 ? pf c uvt ? 0.001 0.15 ?m f c pdt ? 0.001 1.5 ?m f c oct ? 220 560 ? pf
MB3836 6 n electrical characteristics (vcc = 12.6 v, ta = + 25 c) *: standard design value (continued) parameter sym- bol pin no. conditions value unit min typ max over-charge detection block detection voltage v th 2, 7, 8, 9 ta = + 25 c, each cell voltage 4.300 4.325 4.350 v ta = 0 c to + 70 c, each cell voltage 4.280 4.325 4.370 v hysteresis width v h 2, 7, 8, 9 ? 0.14 0.20 0.26 v input current i in 7, 8, 9 each cell voltage = 4.2 v ? 0.1 0.5 m a delay time t d 2covt = 0.01 m f 11.5 23 34.5 ms output voltage v ol 2cout = 1 ma ? 0.75 1.0 v output leakage current i leak 2cout = 13.5 v ? 00.5 m a over- discharge detection, power-fail circuit block detection voltage v th 7, 8, 9, 19 ? 2.695 2.75 2.805 v pf output delay time t d1 19 cuvt = 0.15 m f, vcc = 8.5 v 1 2 3 s pf min pulse width t p 19 cuvt = 0.15 m f, vcc = 8.5 v ? 7 * ? ms output voltage v ol 19 pf = 1 ma ? 0.75 1.0 v output leakage current i leak 19 pf = 13.5 v ? 00.5 m a input threshold voltage v th 3, 18 each cell voltage = 2 v 2.0 3.5 5.0 v input current i in 18 pdwn = 5 v ? 50 100 m a power-down delay time t d2 3cpdt = 1.5 m f, vcc = 8.5 v 10 20 30 s over- current detection block detection voltage v th1 1, 3, 13 voltage between vcc terminal and ocv terminal 0.22 0.30 0.38 v v th2 1, 3, 13 voltage between vcc terminal and ocv terminal 0.45 0.60 0.75 v delay time t d1 3 coct = 560 pf v th2 > vcc - ocv > v th1 4710ms t d2 3 coct = 560 pf vcc - ocv > v th2 250 500 750 m s output voltage v ol 3dout = 1 ma ?? 1.0 v v oh 3dout = - 0.4 ma v cc - 0.4 ?? v cell voltage input block input current at over-charge i in 7, 8, 9 each cell voltage = 4.5 v 22.5 45 67.5 m a short cell detection voltage v th 7, 8, 9 cell voltage without measuring cell = 3.6 v at cout = l ? h ? 0.6 * ? v
MB3836 7 (continued) (vcc = 12.6 v, ta = + 25 c) * : standard design value. parameter sym- bol pin no. conditions value unit min typ max remoting on circuit block input thereshold voltage v tlh 1, 2 ? 0.8 1.4 2.0 v input current i in 1ocv = 13.5 v ? 10 20 m a input resistance at power-down r i 1 ? 480 600 720 w input thereshold voltage v th 20 ? 0.8 1.4 2.0 v input current i in 20 outon = 13.5 v ? 13 17 m a output voltage v oh 5vs = - 4 ma v cc - 0.5 v cc - 0.2 ? v output current i o 5vs = 0 v - 30 ?- 11 ma output leakage current i leak 5 vs = 0 v, each cell voltage = 2 v - 0.5 0 ?m a cell voltage monitoring block voltage gain a v 15 cell voltage = 2.9 v to 4.2 v 0.98 1.0 1.02 v/v input thereshold voltage v th 16, 17 ? 0.8 1.4 2.0 v input current i in 16, 17 msw1 = msw2 = 5 v ? 50 100 m a output source current i oh 15 each cell voltage = 2.9 v, mon = 1.9 v ?- 350 - 180 m a output sink current i ol 15 each cell voltage = 2.9 v, mon = 3.9 v 40 80 ?m a all device power supply current i cc1 6 vcc = 12.6 v, normal state, outon = 5 v ? 75 110 m a i cc2 6 vcc = 8.7 v, normal state, outon = 5 v ? 65 95 m a i cc3 6 vcc = 12.6 v, cell voltage monitoring state ? 130 200 m a i cc4 6 vcc = 6 v, shutting over-discharge state ? 0 * ?m a
MB3836 8 n typical characteristics (continued) 1000 100 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 10 ta = + 25 c 200 180 160 140 120 100 80 60 40 20 0 16 14 12 10 8 6 4 2 0 4.40 4.38 4.36 4.34 4.32 4.30 4.28 4.26 4.24 4.22 4.20 - 40 - 20 0 20 40 60 80 100 1000 100 10 1 0.1 100 1000 10000 100000 ta = + 25 c 100 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 10 ta = + 25 c 100 10 1 0.1 100 1000 10000 ta = + 25 c t d1 vcc - ocv = 0.5 v t d2 vcc - ocv = 1 v power supply current vs.power supply voltage power supply current i cc ( m m m m a) power supply voltage v cc (v) over-charge detection voltage vs. ambient temperature ambient temperature ta ( c) over-charge detection voltage v th (v) delay time on over-charge detection block delay time t d (ms) capacitor for setting delay time c ovt (pf) delay time on over-discharge detection block delay time of alarm output t d (s) capacitor for setting alarm output time c uvt ( m m m m f) delay time on over-discharge detection block power failure permission signal wait time t d (s) capacitor for setting power failure permission signal wait time c pdt ( m m m m f) capacitor for setting delay time c oct (pf) delay time of over-current detection delay time t d1 , t d2 (ms) ta = +25 cbath = vcc h cell voltage = m cell voltage = l cell voltage outon = 5 v cell voltage monitoring state msw1 = open msw2 = 5 v normal state msw1 = msw2 = open typical h cell outon = 5 v bath = vcc batm = 8.4 v batl = 4.2 v
MB3836 9 (continued) - 40 600 540 500 400 300 200 100 0 0 - 20 40 20 80 60 100 power dissipation vs. ambient temperature characteristics ambient temperature ta ( c) power dissipation p d (mw)
MB3836 10 n functional description (1) over-charge detection block when the battery is being charged, the over-charge detection block monitors each cell voltage. if any cell voltage reaches or exceeds the over-charge detection voltage (4.325 v typ) as in figure 1 (see "1. over-charge detection block and cell voltage input block " in " n operation timing chart"), the cout terminal (pin 2) goes h level, after a delay time (23 ms typ) managed by the capacitor (c ovt ) connected between the covt terminal (pin 14) and gnd, to turn off the pch mos fet for external charge control, thereby stopping charging the battery. when all the cell voltages in the over-charge detected state become the over-charge release voltage (4.125 v typ) or less, the cout terminal (pin 2) goes l level to turn on the pch mos fet for external charge control. even when a cell voltage reaches or exceeds the over-charge detection voltage as in figure 2, the cell voltage does not enter the over-charge detected state if it falls below the over-charge detection voltage within the delay time (23 ms typ). (2) cell voltage input block if any cell voltage reaches or exceeds the over-charge detection voltage (4.325 v typ) as in figures 1 and 2 (see "1. over-charge detection block and cell voltage input block" in " n operation timing chart"), the cout terminal (pin 2) goes high to turn off the pch mos fet for external charge control after a delay time (23 ms typ) managed by the capacitor (c ovt ) connected between the covt terminal (pin 14) and gnd. at the same time, the cell voltage input block switch for the cell exceeding the over-charge detection value is turned on to supply the cell voltage input current to that cell so that high-voltage cells are lowered in voltage. when the cell voltage in the over-charge detected state becomes the over-charge release voltage ( 4.125 v typ) or less, the cell voltage input block switch is turned off. (3) over-discharge detection/power fail circuit block when the battery is being discharged, the over-discharge detection/power fail circuit block monitors each cell voltage. if any cell voltage becomes the over-discharge detection voltage (2.75 v typ) as in figure 5 (see "3. over-discharge detection/power fail circuit" in " n operation timing chart"), the pf terminal (pin 19) outputs a l level pf signal to the notebook pc after a pf output delay time (2 s typ) managed by the capacitor (c uvt ) connected between the cuvt terminal (pin 12) and gnd. at the same time, after a power-down delay time (20 s typ) managed by the capacitor (c pdt ) connected between the cpdt terminal (pin 11) and gnd, the dout terminal (pin 3) goes h level to turn off the pch mos fet for external discharge control, thereby stopping discharging the battery. (4) over-current detection block the over-current detection block monitors the discharge current from the battery. it detects an over-current if the potential difference between the vcc and ocv terminals by ron of pch mos fet for external charge control becomes 300 mv or more as in figure 6 (see "4. over-current detection block 1" in " n operation timing chart"). after a delay time (7 ms typ) managed by the capacitor (c oct ) connected between the coct terminal (pin 13) and gnd, the dout terminal (pin 3) goes h level to turn off the pch mos fet for external discharge control, thereby stopping discharging the battery. when the discharge current is large, if the potential difference between the vcc and ocv terminals becomes 600 mv or more as in figure 7 (see "5. over-current detection block 2" in " n operation timing chart"), the dout terminal (pin 3) goes h level to turn off the pch mos fet for external discharge control, thereby stopping discharging the battery, after a power-down delay time (500 m s typ) managed by the capacitor (c oct ) connected between the coct terminal (pin 13) and gnd. note that, if an over-current is detected, the vs terminal (pin 5) goes l level in the same way as when the over- discharge detection function works. as discharging is stopped, the ocv terminal (pin 1) goes l level to
MB3836 11 completely turn off the bias source of this ic, so that the battery pack enters the power-down state. to return from that state, perform recharging operation, or set the ocv terminal (pin 1) to h level. (5) remote on circuit block when the battery pack is detached from the notebook pc, the outon terminal (pin 20) pulled up to the vs terminal (pin 5) on the notebook pc side goes l level to turn off the bias of the over-current detection block. at the same time, the cout terminal (pin 2) and dout terminal (pin 3) go h level to turn off the pch mos fet for external charge/discharge control. even when the outon terminal (pin 20) is l level with charging/discharging off, the ic is operating and the over-discharge detection function is working to protect the battery. if the vs terminal (pin 5) is h level, connecting the battery pack to the main unit makes it readily available. (6) cell voltage monitor block the cell to be monitored can be selected depending on the voltage levels at the msw1 terminal (pin 16) and msw2 terminal (pin 17). when the monitor function is operating, the cell voltage input block switch does not work even when an over-charge is detected. condition of monitoring cell voltage voltage level at msw1 terminal voltage level at msw2 terminal vmon output sw at cell voltage input block ll ? depend on over-charge detection block l h h cell voltage off h l m cell voltage off h h l cell voltage off
MB3836 12 n setting delay time for over-charge detection block for over-charge detection, you can set the delay time from when charging the capacitor (c ovt ) connected to the covt terminal (pin 14) is started and the covt terminal voltage increases until the cout terminal (pin 2) voltage goes h level (with the open-collector output off) with the covt terminal at the threshold voltage. over-charge detection block delay time : t d (s) : = 2.3 c ovt ( m f) n setting pf output delay time for over-discharge detection, you can set the delay time from charging the capacitor (c uvt ) connected to the cuvt terminal (pin 12) is started and the cuvt terminal voltage increases until the pf terminal (pin 19) voltage goes l level with the cuvt terminal at the threshold voltage. pf output delay time : t d1 (s) : = 13.3 c uvt ( m f) n setting power-down delay time you can set the delay time from charging the capacitor (c pdt ) connected to the cpdt terminal (pin 11) is started after l level output to the pf terminal (pin 19) at over-discharge detection and the cpdt terminal voltage increases until the dout terminal (pin 3) voltage goes high with the cpdt terminal at the threshold voltage. power-down delay time : t d2 (s) : = 13.3 c pdt ( m f) after the dout terminal goes h level to stop overdischarging, the ocv terminal (pin 1) goes l level to turn off the entire internal circuitry of the ic so that the circuit current becomes 0 m a. considering the time constant based on the notebook pcs capacitor connected to the ocv terminal, the discharge time constant of cpdt terminal is used to prevent recovery (return) and shutdown (power-down) from being repeated in response to variations in battery voltage. the capacitor connected to the ocv terminal on the notebook pc side requires the restriction expressed below based on the value of the capacitor (c pdt ) connected to the cpdt terminal. ocv terminal external capacitor : c ocv ( m f) < 1790 c pdt ( m f) n setting delay time for over-current detection block for over-current detection when 0.6 v (typ) > vcc - ocv > 0.3 v (typ), you can set the delay time from when charging the capacitor (c oct ) connected to the coct terminal (pin 13) is started and the coct terminal voltage increases until the dout terminal (pin 3) voltage goes h level with the cout terminal at the threshold voltage. over-current detection block delay time : t d1 (s) : = 12.5 c oct ( m f) for over-current detection when vcc - ocv > 0.6 v (typ), you can set the delay time from when charging the capacitor (c oct ) connected to the coct terminal (pin 13) is started and the coct terminal voltage increases until the dout terminal (pin 3) voltage goes h level with the coct terminal at the threshold voltage. over-current detection block delay time : t d2 (s) : = 0.9 c oct ( m f)
MB3836 13 n operation at low voltage if cell voltages cause extreme imbalance or one or more cells enter the short-circuited state (0.6 v typ) or less, the short-circuit cell detection function sets the cout terminal (pin 2) to h level (with the open-collector output off). if the vcc terminal (pin 6) voltage becomes 4.2 v (typ) or less, however, the short-circuit cell detection function is disabled, the cout terminal (pin 2) goes l level, enabling 0 v cell charging, with the ocv terminal (pin 1) at a voltage of 1.4 v (typ) or higher. when vcc is less than 4.2 v, the dout terminal (pin 3) is fixed at h level.
MB3836 14 n operation timing chart 1. over-charge detection block and cell voltage input block (1) when cell 3 does not exceed v th and cells 1 and 2 are lowered in voltage by cell voltage input current and self-discharging if any cell voltage reaches or exceeds the over-charge detection voltage (4.325 v typ), the cout terminal (pin 2) goes h level to turn off the pch mos fet for external charge control, after a delay time (23 ms typ) managed by the capacitor (c ovt ) connected between the covt terminal (pin 14) and gnd, thereby stopping charging the battery. at this time, the cell voltage input block switch is turned on to supply the cell voltage input current to that cell so that high-voltage cells are lowered in voltage. when all the cell voltages in the over-charge detected state become the over-charge release voltage (4.125 v typ) or less, the covt terminal (pin 14) and cout terminal (pin 2) go l level to turn on the pch mos fet for external charge control. when any cell voltage in the over-charge detected state becomes the over-charge release voltage (4.125 v typ) or less, the cell voltage input block switch is turned off. t d (23 ms) v h (0.2 v) v th (4.325 v) (4.125 v) (6.26 v) (45 m a) (0 m a) (45 m a) (0 m a) cell voltage cell voltage input current covt terminal cout terminal cell 2 cell 1 cell 1 cell 2 figure 1
MB3836 15 (2) when the voltage is lowered by cell voltage input current and self-discharge after pulsed charge even when a cell voltage reaches or exceeds the over-charge detection voltage (4.325 v typ), the cell voltage does not enter the over-charge detected state if it falls below the over-charge detection voltage (4.325 v typ) within the delay time (23 ms typ) managed by the capacitor (c ovt ) connected between the covt terminal (pin 14) and gnd. if a cell voltage reaches or exceeds the over-charge detection voltage (4.325 v typ), the cout terminal (pin 2) goes h level to turn off the pch mos fet for external charge control, stopping charging the battery, after a delay time (23 ms typ) managed by the capacitor (covt) connected between the covt terminal (pin 14) and gnd. at this time, the cell voltage input block switch is turned on to supply the cell voltage input current to that cell so that high-voltage cells are lowered in voltage. when all the cell voltages in the over-charge detected state become the over-charge release voltage (4.125 v typ) or less, the covt terminal (pin 14) and cout terminal (pin 2) go l level to turn on the pch mos fet for external charge control. when any cell voltage in the over-charge detected state becomes the over-charge release voltage (4.125 v typ) or less, the cell voltage input block switch is turned off. t d (23 ms) v h (0.2 v) v th (4.325 v) (4.125 v) (6.26 v) (45 m a) (0 m a) cell voltage cell voltage input current covt terminal cout terminal figure 2
MB3836 16 (3) when the outon terminal changes "h" ? ? ? ? "l" ? ? ? ? "h" after detection of an over-charge when the outon terminal (pin 20) changes from h level to l level after detection of an over-charge, the dout terminal (pin 3) goes h level to turn off the pch mos fet for external discharge control, thereby setting the ocv terminal (pin 1) to l level. when the outon terminal (pin 20) changes from h level to l level after all the cell voltages in the over- charge detected state become the over-charge release voltage (4.125 v typ) or less, the cout terminal (pin 2) goes l level to turn on the pch mos fet for external charge control. when the ocv terminal (pin 1) changes from l level to h level at this time, the dout terminal (pin 3) goes l level to turn on the pch mos fet for external discharge control. v th (4.325 v) v h (0.2 v) (4.125 v) (45 m a) (0 m a) (6.26 v) (0 v) (0 v) t d (23 ms) cell voltage cell voltage input current covt terminal cout terminal outon terminal dout terminal ocv terminal vs terminal figure 3
MB3836 17 2. over-charge detection block, discharge detection block, and cell voltage input block when battery is discharged after detection of an over-charge or re-discharged after detection of an over-charge by recharging if a cell voltage reaches or exceeds the over-charge detection voltage (4.325 v typ), the cout terminal (pin 2) goes h level to turn off the pch mos fet for external charge control after a delay time (23 ms typ) managed by the capacitor (c ovt ) connected between the covt terminal (pin 14) and gnd. this stops charging the battery and puts it into the over-charge detected state. when a discharge is started in the over-charge detected state, the ocv terminal voltage is lowered by the body diode voltage of the pch mos fet for external charge control. when the potential difference between the vcc terminal and ocv terminal (pin 1) becomes 300 mv or more, the cout terminal (pin 2) goes l level to turn on the pch mos fet for external charge control and the cell voltage input block switch is turned off at the same time. an over-charge caused by recharging can be detected even with cell voltages remaining above the over-charge release voltage (4.125 v typ). t d (23 ms) t d (23 ms) v h (0.2 v) v th (4.325 v) (4.125 v) (6.26 v) (v cc ) v th (v cc - 0.3 v) (45 m a) (0 m a) discharge start cell voltage input current covt terminal cout terminal ocv terminal charge start discharge start cell voltage figure 4
MB3836 18 3. over-discharge detection/power fail circuit when no h level signal is input to the pdwn terminal after over-discharge detection if any cell voltage becomes the over-discharge detection voltage (2.75 v typ), the pf terminal (pin 19) outputs a l level pf signal to the notebook pc after a pf output delay time (2 s typ) managed by the capacitor (c uvt ) connected between the cuvt terminal (pin 12) and gnd. at the same time, after a power-down delay time (20 s typ) managed by the capacitor (c pdt ) connected between the cpdt terminal (pin 11) and gnd, the dout terminal (pin 3) goes h level to turn off the pch mos fet for external discharge control, thereby stopping discharging the battery. the vs terminal (pin 5) goes l level at this time. as discharging is stopped, the ocv terminal (pin 1) goes l level to completely turn off the bias source in the ic. that is, an over-discharge state is detected when a cell voltage does not return to the over-discharge detection voltage (2.75 v typ) or more within the power-down delay time (20 s typ), an over-discharge state is detected. when the ocv terminal (pin 1) goes h level, the dout terminal (pin 3) goes l level to turn on the pch mos fet for external discharge control and the vs terminal (pin 5) goes h level. if the cell voltage remains not exceeding the over-discharge detection voltage (2.75 v typ) at this time, the pf terminal (pin 19) outputs a l level pf signal to the notebook pc again after a pf output delay time (2 s typ) managed by the capacitor (c uvt ) connected between the cuvt terminal (pin 12) and gnd. if the cell voltage reaches or exceeds the over- discharge detection voltage (2.75 v typ) within the power-down delay time (20 s typ), however, the pf terminal goes h level and an over-discharge state is not detected.
MB3836 19 v th (2.75 v) (4.9 v) (4.9 v) 0 v 0 v 0 v 0 v t d1 (2 s) t d2 (20 s) t d1 (2 s) cell voltage cuvt terminal pf terminal cpdt terminal pdwn terminal dout terminal ocv terminal outon terminal internal bias : off vs terminal figure 5 charge start
MB3836 20 4. over-current detection block 1 when a discharge current is relatively small as an over-current, if the potential difference between the vcc terminal and ocv terminal (pin 1) by ron of the pch mos fet for external charge control becomes 300 mv or more, the capacitor (c oct ) connected between the coct terminal (pin 13) and gnd is charged. no over- current is detected if the ocv terminal voltage returns to the battery voltage level within the delay time (7 ms typ). if the potential difference between the vcc terminal and ocv terminal (pin 1) by ron of the pch mos fet for external charge control becomes 300 mv or more again, an over-current is detected after a delay time (7 ms typ) managed by the capacitor (c oct ) connected between the coct terminal (pin 13) and gnd. at this time, the dout terminal (pin 3) goes h level to turn off the pch mos fet for external discharge control and the bias source in the ic is completely turned off as well. recharging can be restarted by setting the ocv terminal (pin 1) to h level to set the dout terminal (pin 3) to l level and vs terminal (pin 5) to h level, respectively. (v cc ) v th (v cc - 0.3 v) v th (v cc - 0.6 v) 0 v (5.8 v) 0 v t d (7 ms) ocv terminal coct terminal dout terminal vs terminal charge start internal bias : off figure 6
MB3836 21 5. over-current detection block 2 when a discharge current is relatively large as an over-current, if the potential difference between the vcc terminal and ocv terminal (pin 1) by ron of the pch mos fet for external charge control becomes 300 mv or more, the capacitor (c oct ) connected between the coct terminal (pin 13) and gnd is charged. no over- current is detected if the ocv terminal voltage returns to the battery voltage level within the delay time (7 ms typ). if the potential difference between the vcc terminal and ocv terminal (pin 1) of the pch mos fet for external charge control becomes 600 mv or more, an over-current is detected after a delay time (500 ms typ) managed by the capacitor (c oct ) connected between the coct terminal (pin 13) and gnd. at this time, the dout terminal (pin 3) goes h level to turn off the pch mos fet for external discharge control, both of the vs terminal (pin 5) and ocv terminal (pin 1) go l level, and the bias source in the ic is completely turned off as well. recharging can be restarted by setting the ocv terminal (pin 1) to h level to set the dout terminal (pin 3) to l level and vs terminal (pin 5) to h level, respectively. (v cc ) v th (v cc - 0.3 v) v th (v cc - 0.6 v) 0 v (5.8 v) 0 v t d (500 m s) ocv terminal coct terminal dout terminal vs terminal charge start internal bias : off figure 7
MB3836 22 n treatment when voltage monitor function is not used when the voltage monitor function is not used, connect the msw1 terminal (pin 16) and msw2 terminal (pin 17) to gnd by taking their shortest ways and leave the vmon terminal (pin 15) open. n note on vs terminal if the battery is charged through the body diode of the internal pch mos fet connected to the vs terminal (pin 5), the over-charge protection function cannot be disabled. be careful not to apply a voltage equal to or higher than the vcc terminal voltage to the vs terminal. n note on electrostatic application this ic has a built-in function to set icc to 0 m a in power-down mode to extend the battery life. as a charger is required to return the ic from power-down mode, use meticulous care not to let it malfunction, for example, with applied static electricity. to prevent electrostatic noise from coming into each input pin of the ic, it is advisable to lower impedance, for example, by adding a capacitor. the capacitor used for this purpose should be placed as close to the ic as possible. 17 16 15 msw2 msw1 vmon open when voltage monitor function is not used
MB3836 23 n i/o terminal equivale circuit vcc gnd ocv coct 2 k w 300 k w 300 k w 6 10 1 3 13 vcc gnd cuvt pf cpdt pdwn 2 k w 500 k w 2 k w 1 k w 100 k w 20 k w 12 19 11 18 vcc gnd covt cout 2 k w 1 4 2 gnd batl batm x1 x1 100 k w 100 k w bath x1 100 k w 7 8 9 gnd vs ocv outon 600 w 50 w vcc 5 2 0 5 700 k w 1 m w vcc gnd vmon 100 k w 1 7 15 100 k w 100 k w 100 k w 1 6 msw2 msw1 [over-current detection block] esd protection element [over-discharge detection/power fail circuit block] [over-charge detection block] [cell voltage input block] [remote on circuit block] [cell voltage monitor block]
MB3836 24 n application example 600 mv - + - + 1 1 1 + - + - + - - - - + 6 7 8 9 10 15 16 17 13 14 11 12 18 19 20 5 1 vcc bias on/off 100 k w 100 k w bath c1 r1 0.1 m f batm batl gnd vmon c9 4700 pf msw1 c10 4700 pf msw2 c11 4700 pf coct covt cpdt cuvt pdwn pf vs ocv cout dout m2 m1 300 mv 4.325 v ( 0.6%) 2.75 v ( 2%) latch2 latch1 latch3 bias on/off 600 w 2 3 c6 560 pf c7 0.01 m f c2 1.5 m f c12 0.22 m f c5 0.15 m f r7 100 w r8 r4 1 m w zd1 18 v c14 0.1 m f c15 c13 r6 10 w r5 1 m w r14 10 k w r13 10 k w r9 1 m w 0.1 m f ( + ) (g) outon 100 k w 0.1 m f 1 k w 1 k w 1 k w r2 r3 100 k w (7 ms) (500 m s) pf output time (2 s) [cell voltage input block] [over-discharge detection/ power fail circuit block] [remote on circuit block] delay circuit pch mos fet for discharge control delay circuit (23 ms) reset decoder reference volt- age source power down delay time (20 s) [over-current de- tection block] pch mos fet for charge control h cell m cell l cell litium-ion battery [ over-charge detection block] [cell voltage monitor block] reset reset note pc side
MB3836 25 n parts list note: vishay siliconix : vishay intertechnology, inc. toshiba : toshiba corporation n usage precaution printed circuit board ground lines should be set up with consideration for common impedance. take appropriate static electricity measures. ? containers for semiconductor materials should have anti-static protection or be made of conductive material. ? after mounting, printed circuit boards should be stored and shipped in conductive bags or containers. ? work platforms, tools, and instruments should be properly grounded. ? working personnel should be grounded with resistance of 250 k w to 1 m w between body and ground. component item specification vendor parts no. m1, m2 fet vds = - 30 v vishay siliconix si4425dy zd1 diode 200 mw, 18 v 7% toshiba 02cz18-y c1 c2 c5 c6 c7 c9, c10, c11 c12 c13, c14, c15 ceramics condenser ceramics condenser ceramics condenser ceramics condenser ceramics condenser ceramics condenser ceramics condenser ceramics condenser 0.1 m f 1.5 m f 0.15 m f 560 pf 0.01 m f 4700 pf 0.22 m f 0.1 m f 25 v (10%) 16 v (10%) 16 v (10%) 50 v (5%) 25 v (10%) 25 v (10%) 25 v (10%) 25 v (10%) ?? r1, r2, r3 r4, r5, r9 r6 r7 r8 r13, r14 resistor resistor resistor resistor resistor resistor 1 k w 1 m w 10 w 100 w 100 k w 10 k w 1/16 w, 5% 1/16 w, 5% 1/16 w, 5% 1/16 w, 5% 1/16 w, 5% 1/16 w, 5% ??
MB3836 26 n ordering information part number package remarks MB3836pfv 20-pin plastic ssop (fpt-20p-m03)
MB3836 27 n package dimension 20-pin plastic ssop (fpt-20p-m03) note 1) * 1: resin protrusion. (each side: +0.15 (.006) max). note 2) * 2: these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm (inches). note: the values in parentheses are reference values. c 2003 fujitsu limited f20012s-c-4-6 6.500.10(.256.004) 4.400.10 6.400.20 (.252.008) (.173.004) .049 C.004 +.008 C0.10 +0.20 1.25 (mounting height) 0.10(.004) 0.65(.026) 0.240.08 (.009.003) 1 10 20 11 "a" 0.100.10 (stand off) 0.170.03 (.007.001) m 0.13(.005) (.004.004) details of "a" part 0~8 ? (.024.006) 0.600.15 (.020.008) 0.500.20 0.25(.010) lead no. index * 1 * 2
MB3836 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0310 ? fujitsu limited printed in japan

▲Up To Search▲

Price & Availability of MB3836

	To Download MB3836 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .